No, a microarchitect does not build tiny houses

portrait I am currently working as a researcher ("Chargé de Recherche") at TIMA, a CNRS laboratory in Grenoble, within the System Level Synthesis (SLS) team. My research focuses on all aspects of high performance general purpose processors.

Previously, I was working at Microsoft Raleigh from December 2018 until August 2020 were I contributed to MSFT's custom designs needs (notably, control system of a Quantum Computer).

Before that, I was with Qualcomm Datacenter Technologies Raleigh from January 2017 to June 2018 to work on future generation ARM microprocessors (Centriq). My work in the QDT performance modelling group revolved — mostly — around efficient instruction delivery mechanisms.

Until 2017, and ignoring my 1-day tenure at Intel France as a research scientist, I was a research engineer with the PACAP INRIA research team in Rennes. My research focused on core microarchitecture and in particular, how to increase sequential performance. This included continuing the work I began during my Ph.D., i.e., revisiting a speculation technique that was introduced in the mid 90's: Value Prediction (VP).

VP has regained some traction recently as a way to increase sequential performance and may happen in future processors since Dennard Scaling has ended and Moore's Law is not doing too well. This might be why it was awarded the MICRO Test-of-time award in 2017. You might also be interested in the Championship Value Prediction.