Topics

• Performance-oriented microarchitecture.
• Efficiency-oriented microarchitecture.
• Value Prediction.
• Security.
• Tools.

Tools

• A. Perais, Championship Value Prediction 1 Public Traces from CVP1, 2022. Consider reading Rebasing Microarchitectural Research with Industry Tracess before using.

• A. Perais, Championship Value Prediction 1 Secret Traces from CVP1, 2022. Consider reading Rebasing Microarchitectural Research with Industry Tracess before using.

Peer Reviewed Conferences

• S. Singh, A. Perais A. Jimborean and A. Ros, Alternate Path µ-op Cache Prefetching. In Proc. of the 51th International Symposium on Computer Architecture (ISCA51), Buenos Aires, 2024, to appear

• A. Perais and R. Sheikh, Branch Target Buffer Organizations. In Proc. of the 56th International Symposium on Microarchitecture (MICRO56), Toronto, 2023.

• J. Feliu, A. Perais, D. A. Jiménez and A. Ros, Rebasing Microarchitectural Research with Industry Tracess. In Proc. of the International Symposium on Workload Characterization (IISWC 2023), Ghent, 2023.

• S. Singh, A. Perais, A. Jimborean and A. Ros, Exploring Instruction Fusion Opportunities in General Purpose Processors. In Proc. of the 55th International Symposium on Microarchitecture (MICRO55), Chicago, 2022.

• A. Asgharzadeh, J. M. Cebrian, A. Perais, S. Kaxiras and A. Ros, Free Atomics: Hardware Atomic Operations without Fences. In Proc. of the 49th International Symposium on Computer Architecture (ISCA49), New York, 2022,. Best paper session.

• A. Perais, Leveraging Targeted Value Prediction to Unlock New Hardware Strength Reduction Potential. In Proc. of the 54th International Symposium on Microarchitecture (MICRO54), Athens, 2021.

• Moritz Lipp, Vedad Hadžić, Michael Schwarz, Arthur Perais, Clémentine Maurice and Daniel Gruss, Take A Way: Exploring the Security Implications of AMD's Cache Way Predictors. In Proc. of the 15th ASIA Conference on Computer and Communications Security (AsiaCCS15), Taipei, 2020.

• A. Perais, R. Sheikh, L. Yen, M. McIlvaine and R. D. Clancy, Elastic Instruction Fetching. In Proc. of the 25th International Conference on High Performance Computer Architecture (HPCA25), Washington, 2019. Slides.

• A. Perais and A. Seznec, Cost effective speculation with the omnipredictor. In Proc. of the 18th International Conference on Parallel Architectures and Compilation Techniques (PACT18), Limassol, 2018. Slides. Best paper award.

• V. Reddy, R. Sheikh, A. Perais and H. W. Cain, SPF: Selective Pipeline Flush. In Proc. of the 36th International Conference on Computer Design (ICCD36), Orlando, 2018.

• A. Perais, F. A. Endo and A. Seznec, Register Sharing for Equality Prediction. In Proc. of the 49th International Symposium on Microarchitecture (MICRO49), Taipei, 2016. Slides.

• A. Perais and A. Seznec, Cost-Effective Physical Register Sharing. In Proc. of the 22th International Symposium on High Performance Computer Architecture (HPCA22), Barcelona, 2016. Slides.

• A. Sembrant, T. Carlson, E. Hagersten, D. Black-Schaffer, A. Perais, A. Seznec, P. Michaud, Long Term Parking (LTP): Criticality-aware Resource Allocation in OOO Processors. In Proc. of the 48th International Symposium on Microarchitecture (MICRO48), Honolulu, 2015. Slides.

• A. Perais, A. Seznec, P. Michaud, A. Sembrant and E. Hagersten, Cost-Effective Speculative Scheduling in High Performance Processors. In Proc. of the 42th International Symposium on Computer Architecture (ISCA42), Portland, 2015. Slides, Fast Forward Slides

• A. Perais and A. Seznec. BeBoP: A Cost Effective Predictor Infrastructure for Superscalar Value Prediction. In Proc. of the 21th International Symposium on High Performance Computer Architecture (HPCA21), San Francisco, 2015. Slides.

• A. Perais and A. Seznec. EOLE: Paving the Way for an Effective Implementation of Value Prediction. In Proc. of the 41th International Symposium on Computer Architecture (ISCA41), Minneapolis, 2014. Slides, Fast Forward Slides. IEEE Micro's Top Picks.

• A. Perais and A. Seznec. Practical Data Value Speculation for Future High-end Processors. In Proc. of the 20th International Symposium on High Performance Computer Architecture (HPCA20), Orlando, 2014. Slides. Best paper session.

Journal

• C. S. Deshpande, Arthur Perais and F. Pétrot, Toward Practical 128-bit General Purpose Microarchitectures. in IEEE Computer Architecture Letters, June 2023.

• Arthur Perais, A Case for Speculative Strength Reduction. in IEEE Computer Architecture Letters, January 2021. Best of CAL.

• F. A. Endo, A. Perais and A. Seznec. On the interactions between value prediction and compiler optimizations in the context of EOLE in ACM Transactions on Architecture and Code Optimization, July 2017.

• A. Perais and A. Seznec. Storage-Free Memory Dependency Prediction in IEEE Computer Architecture Letters, November 2016.

• A. Perais and A. Seznec. EOLE: Combining Static and Dynamic Scheduling through Value Prediction to Reduce Complexity and Increase Performance. In ACM Transcations on Computer Systems, May 2016.

• A. Perais and A. Seznec. EOLE: Toward a Practical Implementation of Value Prediction. In IEEE Micro, Special Issue: Micro's Top Picks from Computer Architecture Conferences, June 2015.

PhD Thesis

• Increasing the Performance of Superscalar Processors through Value Prediction. September 2015.

Other

• "La prédiction de valeurs, c'est comme monter une étagère sans lire le manuel", February 2017.

Google Scholar page or DBLP *might* be more up to date.